Experimental evaluation and improvements to linear scan register allocation

We report our experience from implementing and experimentally evaluating the performance of various register allocation schemes, focusing on the recently proposed linear scan register allocator. In particular, we describe in detail our implementation of linear scan and report on its behavior both on register-rich and on register-poor computer architectures. We also extensively investigate how different options to the basic algorithm and to the compilation process as a whole affect compilation times and quality of the produced code. In a nutshell, our experience is that a well-tuned linear scan register allocator is a good choice on register-rich architectures. It performs competitively with graph coloring based allocation schemes and results in significantly lower compilation times. When compilation time is a concern, such as in just-in-time compilers, it can also be a viable option on register-poor architectures. Copyright c © 2003 John Wiley & Sons, Ltd.